Arrays of analog-to-digital converters operating in parallel comprise a plurality of analog-to-digital converters which digitize an analog signal in parallel, but with a certain temporal offset. The individual digital signals are then recombined by means of a multiplexer, thereby effectively achieving a higher sampling rate than that of the individual analog-to-digital converters. Converter arrays of this type are also called TIADCs (=time interleaved analog-to-digital converters).
In the simplest case of a TIADC, two analog-to-digital converters are connected in parallel, alternately sample a common analog input signal and digitize it. As a result, the sampling or conversion rate of the overall system appears doubled compared with the sampling rate of the individual analog-to-digital converters.
In the more general case, by increasing the number of analog-to-digital converters operating in parallel or by increasing the number of channels, in the case of N analog-to-digital converters it is possible to increase the effective sampling rate of the converter array to N times the sampling rate of an individual analog-to-digital converter. In the case of such arrays, however, there is the difficulty that any type of inequality among the individual converters leads to conversion errors. By way of example, different offset values of the various analog-to-digital converters lead to disturbing sounds at frequencies comprising whole divisors of the sampling frequency. Different nonlinearities of the channels, differences in gain, deviations from the ideal sampling instant or a different bandwidth of the analog-to-digital converters also lead to undesirable disturbances.
The text below discusses in particular the adjustment of the individual sampling instants of the respective analog-to-digital converters in a TIADC.
FIG. 1 shows a converter array or TIADC according to the prior art.
N analog-to-digital converters A/D1, A/D2, . . . A/DN are provided, each having an analog input E1, E2, . . . EN, a digital output A1, A2, . . . AN and an input C1, C2, . . . CN for a respective clock signal CLK1′, CLK2′, . . . CLKN′. A common analog input signal VIN is applied to the analog inputs E1, E2 . . . EN. The analog-to-digital converters A/D1, A/D2, A/DN in each case supply digital intermediate signals Z1, Z2, ZN at their outputs A1, A2, AN, which intermediate signals are switched through as digital output signal ZD of the TIADC by a multiplexer MUX connected downstream.
A clock generator CLKG generates a global clock signal CLK, which is passed to a Delay Locked Loop DLL, which generates therefrom an N phase clock or N clock signals CLK1, CLK2 . . . CLKN which in each case have the same clock period T as the global clock signal CLK but are in each case delayed by a time offset of T/N=ΔT.
These clock signals CLK1, CLK2, CLKn are in each case passed via a tunable delay element V1, V2, VN, by way of example in each case a Vernier element, as tuned clock signals CLK1′, CLK2′, CLKN′ to the inputs C1, C2, . . . CN of the individual analog-to-digital converters A/D1, A/D2, A/DN. The tunable delay elements V1, V2, V3 are set in such a way that clock signals CLK1, CLK2, CLKN that deviate from the ideal clock are delayed to a greater or lesser extent in order to compensate for the error.
As is described in K. Poulton et al.: “A 4GS/s 8b ADC in 0.35 m CMOS”, ISSCC 2002, pages 166–167, the optimum sampling instants or the optimum time offsets which are determined by the respective clock signals CLK1′, CLK2′, CLKN′ may be set by applying a pulsed wave as input signal VIN and Fourier analysis of the digital intermediate signals Z1, Z2, ZN. What is disadvantageous about the prior art solution for delay adjustment is, in particular, that the variable delay elements V1, V2, . . . VN have to be kept available N-fold and have to be individually drivable. A considerable additional outlay on circuitry is therefore required. Moreover, the tunable delay elements represent additional noise sources and may cause shallower clock edges. This leads to an increased timing jitter and reduces the performance of the converter array according to the prior art.
Anderson et al. “Verification of a Blind Mismatch Error Equalization Method for Randomly Interleaved ADCs using a 2.5 V/12b/30 MSs PSAADC”, ESSCIRC 2003, pages 473–476, describes a method for attenuating disturbance effects due to misadjusted analog-to-digital converters in TIADCs. According to this method, a further M additional analog-to-digital converters are provided as well as the N parallel analog-to-digital converters. Since the entire converter array is intended to yield a sampling rate that is N times higher than that of each individual analog-to-digital converter, the M additional analog-to-digital converters are used to achieve randomization. For a converter cycle, N converters are randomly selected from the N plus M converters and their conversion result is switched through as digital output signal of the converter array by the multiplexer. This results in a random distribution, inter alia of the offset errors. This method also requires a huge additional outlay on circuitry since additional analog-to-digital converters have to be kept available.